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rev. 1.4 june 2012 www.aosmd.com page 1 of 15 AOZ1025D ezbuck? 8a synchronous buck regulator general description the AOZ1025D is a high efficiency, simple to use, buck regulator, capable of up to 8a with an external low side mosfet. the AOZ1025D works from a 4.75v to 16v input voltage range, the AOZ1025D comes in a 5 x 4 dfn-16 package and is rated over a -40c to +85c ambient temperature range. features ? 4.75 to 16v operating input voltage range ? synchronous rectification: integrated high side mosfet ? high efficiency: up to 95% ? internal soft start ? output voltage adjustable to 0.8v ? up to 8a continuous output current ? fixed 500khz pwm operation ? cycle-by-cycle current limit ? short-circuit protection ? thermal shutdown ? small size 5 x 4 dfn-16 package applications ? point of load dc/dc conversion ? desktops/graphics cards ? pcie graphics cards ? set top boxes ? blu-ray and hd-dvd?recorders ? lcd tvs typical application figure 1. 1.2v/8a synchronous buck regulator lx vin good vout 5v dc vin = 12v fb ngate pgnd en comp agnd c1, c2 22f ceramic c3, c4, c5 22f ceramic r1 r2 r c c c l1 2.2h AOZ1025D
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 2 of 15 ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/media/aosgreenpolicy.pdf for additional information. pin configuration pin description part number ambient temperature range package environmental AOZ1025Dil -40c to +85c 5 x 4 dfn-16 green product lx lx lx ngate pgood pgnd en comp lx vin vin vin vin agnd fb nc 5 x 4 dfn-16 (top thru view) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 agnd lx pin number pin name pin function 1 lx pwm output connection to inductor. thermal connection for output stage. 2, 3, 4, 5 v in supply voltage input. when vin rises above the uvlo threshold the device starts up. 6 agnd reference connection for controller section. also used as thermal connection for controller section. electrically needs to be connected to pgnd 7 fb the fb pin is used to determine the output vo ltage via a resistor divider between the output and gnd. 8 nc not connected 9 comp external loop compensation pin. 10 en the enable pin is active high. do not leave it open. 11 pgnd power ground. electrically needs to be connected to agnd. 12 pgood power good. open drain. use resistor to pull up to 5v supply. 13 ngate low side mosfet driver; connect it to the gate of external low side mosfet. 14, 15, 16 lx pwm output connection to inducto r. thermal connection for output stage.
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 3 of 15 block diagram absolute maximum ratings exceeding the absolute maximum ratings may damage the device. note: 1. devices are inherently esd s ensitive, handling precautions are required. human body model rating: 1.5k ? in series with 100pf. recommend operating ratings the device is not guaranteed to operate beyond the maximum operating ratings. note: 2. the value of ? ja is measured with the device mounted on 1-in 2 fr-4 board with 2oz. copper, in a still air environment with t a = 25c. the value in any given application depends on the user's specific board design. 500khz/68khz oscillator agnd pgnd vin en fb pgood comp lx ldrv otp internal +5v ilimit pwm control logic 5v ldo regulator uvlo & por softstart reference & bias 0.8v q1 pwm comp level shifter + fet driver isen eamp + ? + ? frequency foldback comparator 0.2v + ? + ? + over voltage comparator 0.72v + ? 0.96v 0.86v + ? parameter rating supply voltage (v in ) 18v lx to agnd -0.7v to v in +0.3v en to agnd -0.3v to v in +0.3v fb to agnd -0.3v to 6v comp to agnd -0.3v to 6v pgnd to agnd -0.3v to +0.3v junction temperature (t j ) +150c storage temperature (t s ) -65c to +150c esd rating (1) 2kv parameter rating supply voltage (v in ) 4.75v to 16v output voltage range 0.8v to v in ambient temperature (t a ) -40c to +85c package thermal resistance 5 x 4 dfn-16 ( ? ja ) (2 ) 50c/w package thermal resistance 5 x 4 dfn-16 ( ? jc ) (2 ) 5c/w
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 4 of 15 electrical characteristics t a = 25c, v in = v en = 12v, v out = 1.2v unless otherwise specified (3 ) note: 3. specification in bold indicate an ambient temperature range of -40c to + 85c. these specifications are guaranteed by design. symbol parameter conditions min. typ. max. units v in supply voltage 4.75 16 v v uvlo input under-voltage lockout threshold v in rising v in falling 4.1 3.7 v i in supply current (quiescent) i out = 0, vfb = 1.2v, v en > 1.2v 1.2 3 ma i off shutdown supply current v en = 0v 30 a v fb feedback voltage 0.788 0.8 0.812 v load regulation 0.5 % line regulation 0.2 % i fb feedback voltage input current 200 na v en en input threshold off threshold on threshold 2 0.6 v v hys en input hysteresis 100 mv modulator f o frequency 350 500 600 khz d max maximum duty cycle 100 % d min minimum duty cycle 6% error amplifier voltage gain 500 v / v error amplifier transconductance 200 a / v protection i lim current limit 10 a over-temperature shutdown limit t j rising t j falling 150 100 c v pr output over-voltage protect ion threshold off threshold on threshold 960 860 mv t ss soft start interval 3 4 6.5 ms power good v olpg pg low voltage i ol = 1ma 0.5 v pg leakage 1a v pgl pg threshold voltage -12 -10 -8 % pg threshold voltage hysteresis 3 % pg delay time 128 s output stage high-side switch on-resistance v in = 12v 43 57 m ? low side driver pull-up resistance 20 ? pull-up resistance 7 ?
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 5 of 15 maximum output current maximum output cu rrent of buck converters such as AOZ1025D is related with driving capability and thermal condition. AOZ1025D?s driving voltage varies with the input voltage. when input voltage is higher than 6.5v, the driver inside the AOZ1025D can drive both high side and low side mosfets to deliver 8a output current; but when the input voltage is 5v, the recommended maximum output current is de-rated to 6a. the output voltage within a fixed input voltage directed determines the turn-on ratio of integrated pmos, and thus the thermal condition of AOZ1025D during the operation. the fo llowing diagrams show the safe operation region of aoz1025 operating at v in = 5v, and v in = 12v respectively. input voltage vs. maximum output current AOZ1025D?s driving voltage varies with the input voltage.twh en input voltage is higher than 6.5v, the driver inside the AOZ1025D can drive both high side and low side mosfets to deliver 8a output current; but when the input voltage is 5v, the recommended maximum output current is de-rated to 6a.tthe following diagram shows relations of the input voltage and the maximum output current of AOZ1025D. 0 1 2 3 4 5 6 7 8 9 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 0 1 2 3 4 5 6 7 0.8 1.3 1.8 2.3 2.8 3.3 3.8 v in = 12v safe operation region output voltage (v) output current (a) v in = 5v safe operation region output voltage (v) output current (a) 2 3 4 5 6 7 8 9 5 6 7 8 9 10 11 12 13 14 15 16 input voltage vs. maximum output current voltage (v) current (a)
rev. 1.4 june 2012 www.aosmd.com page 6 of 15 AOZ1025D efficiency the efficiency was measured based on figure 1 with the low-side external mosfet (ao4722). 70 75 80 85 90 95 100 efficiency (v in = 5v) 01234 v o = 1.1v v o = 1.8v v o = 3.3v v o = 1.1v v o = 1.8v v o = 3.3v v o = 5.0v 56 current (a) efficiency (%) 70 75 80 85 90 95 100 efficiency (v in = 12v) 012345678 current (a) efficiency (%) 70 75 80 85 90 95 100 efficiency (v in = 5v) 01234 v o = 1.1v v o = 1.8v v o = 3.3v v o = 1.1v v o = 1.8v v o = 3.3v v o = 5.0v 56 current (a) efficiency (%) 70 75 80 85 90 95 100 efficiency (v in = 12v) 012345678 current (a) efficiency (%)
rev. 1.4 june 2012 www.aosmd.com page 7 of 15 AOZ1025D detailed description the AOZ1025D is a current-mode step down regulator with integrated high-side pmos switch. it operates from a 4.75v to 16v input voltage range and supplies up to 8a of load current. the duty cycle can be adjusted from 6% to 100% allowing a wide range of output voltage. features include enable control, power-on reset, input under voltage lockout, output over voltage protection, fixed internal soft-start and thermal shut down. enable and soft start the AOZ1025D has internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. a soft start process begins when the input voltage rises to 4.0v and voltage on en pin is high. in soft start process, the output voltage is ramped to regulation voltage in typically 4ms. the 4ms soft start time is set internally. the voltage on en pin must rise above 1.8v to enable the AOZ1025D. when voltage on en pin falls below 0.6v, the AOZ1025D is disabled. steady-state operation under steady-state conditions, the converter operates in fixed frequency and continuous-conduction mode (ccm). the AOZ1025D integrates an internal p-mosfet as the high-side switch. inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power mosfet. output voltage is divided down by the external voltage divider at the fb pin. the difference of the fb pin voltage and reference is amplified by the internal transconductance error amplifier. the error voltage, which shows on the comp pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at pwm comparator input. if the current signal is less than the error voltage, the internal high-side switch is on. the inductor current flows from the input through the inductor to the output. when the current signal exceeds the error voltage, the high-side switch is off. the inductor current is freewheeling through the external low-side n-mosfet switch to output. the internal adaptive fet driver guarantees no turn on overlap of both high-side and low-side switch. the AOZ1025D uses an external freewheeling nmosfet to realize synchronous rectification. it greatly improves the converter efficiency and reduces power loss in the low-side switch. the AOZ1025D uses a p-channel mosfet as the high-side switch. it save s the bootstrap capacitor normally seen in a circuit which is using an nmos switch. switching frequency the AOZ1025D switching frequency is fixed and set by an internal oscillator. the practical switching frequency could range from 350 khz to 600 khz due to device variation. output voltage programming output voltage can be set by feeding back the output to the fb pin by using a resistor divider network. in the application circuit shown in figure 1. the resistor divider network includes r 1 and r 2 . usually, a design is started by picking a fixed r 2 value and calculating the required r 1 with equation: some standard value of r1, r2 and most used output voltage values are listed in table 1. table 1. the combination of r 1 and r 2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. v o (v) r 1 (k ? ) r 2 (k ? ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.6 10 5.0 52.3 10 v o 0.8 1 r 1 r 2 ------ - + ?? ?? ?? ? =
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 8 of 15 protection features the AOZ1025D has multiple protection features to prevent system circuit damage under abnormal conditions. over current protection (ocp) the sensed inductor current si gnal is also used for over current protection. since the AOZ1025D employs peak current mode control, the comp pin voltage is propor- tional to the peak inductor current. the comp pin voltage is limited to be between 0.4v and 2.5v internally. the peak inductor current is automatically limited cycle by cycle. when the output is shorted to ground under fault conditions, the inductor current decays very slow during a switching cycle because of v o = 0v. to prevent catastrophic failure, a secondary current limit is designed inside the AOZ1025D. the measured inductor current is compared against a preset voltage which represents the current limit. when the output current is more than current limit, the high side switch will be turned off and en pin will be pulled down. t he converter will initiate a soft start once the over-current condition disappears. output over voltage protection (ovp) the AOZ1025D monitors the feedback voltage: when the feedback voltage is higher than 960mv, it immediate turns-off the pmos to protect the output voltage overshoot at fault condition. when feedback voltage is lower than 840mv, the pmos is allowed to turn on in the next cycle. under-voltage lock-out (uvlo) a power-on reset circuit monitors the input voltage. when the input voltage exceeds 4v, the converter starts operation. when input voltage falls below 3.7v, the converter will be shut down. thermal protection an internal temperature sensor monitors the junction temperature. it shuts down the internal control circuit and high side pmos if the junction temperature exceeds 150c. the regulator will rest art automatica lly under the control of soft-start circuit when the junction temperature decreases to 100c. power good the output of power-good is an open drain n-channel mosfet, which supplies an active high power good stage. a pull-up resistor should connect this pin to a dc power trail with maximum voltage no higher than 6v. the AOZ1025D monitors the fb voltage: when fb pin voltage is lower than 90% of the normal voltage, n-channel mosfet turns on and the power-good pin is pulled low, which indicates the power is abnormal. application information the basic AOZ1025D applicat ion circuit is show in figure 1. component selection is explained below. input capacitor the input capacitor must be connected to the v in pin and pgnd pin of AOZ1025D to maintain steady input voltage and filter out the pulsing input current. the voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. the input ripple voltage can be approximated by equation below: since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. for a buck circuit, the rms value of input capacitor current can be calculated by: if we let m equal the conversion ratio: the relationship between the input capacitor rms current and voltage conversion ratio is calculated and shown in figure 2. it can be seen that when v o is half of v in , c in is under the worst current stress. the worst current stress on c in is 0.5 x i o . figure 2. i cin vs. voltage conversion ratio ? v in i o fc in ? ----------------- 1 v o v in -------- - ? ?? ?? ?? v o v in -------- - ? ? = i cin_rms i o v o v in -------- - 1 v o v in -------- - ? ?? ?? ?? ? = v o v in -------- - m = 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 m i cin_rms (m) i o
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 9 of 15 for reliable operation and best performance, the input capacitors must have current rating higher than i cin_rms at worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high current rating. depending on the application circuits, other low esr tantalum capacitor may also be used. when selecting ceramic capacitors, x5r or x7r type dielectric ceramic capacitors should be used for their better temperature and voltage characteristics. note that the ripple current rating from capacitor manufactures are based on certain amount of life time. further de-rating may be necessary in practical design. inductor the inductor is used to supply constant current to output when it is driven by a switching voltage. for given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: the peak inductor current is: high inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. low ripple current reduces inductor core losses. it also reduces rms current through inductor and switches, which results in less conduct ion loss. usually, peak to peak ripple current on inductor is designed to be 20% to 40% of output current. when selecting the inductor, ma ke sure it is able to handle the peak current without saturation even at the highest operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on inductor need to be checked for thermal and efficiency requirements. surface mount inductors in different shape and styles are available from coilcraft, elytone and murata. shielded inductors are small and radiate less emi noise. but they cost more than unshielded inductors. the choice depends on emi requirement, price and size. output capacitor the output capacitor is selected based on the dc output voltage rating, output ripple voltage specification and ripple current rating. the selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. de-rating needs to be considered for long term reliability. output ripple voltage specification is another important factor for selecting the output capacitor. in a buck con- verter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and esr. it can be calculated by the equation below: where, c o is output capacitor value, and esr co is the equivalent series resistance of the output capacitor. when low esr ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. output ripple is mainly caused by capacitor value and inductor ripple current. the output ripple voltage calculation can be simplified to: if the impedance of esr at switching frequency dominates, the output ripple voltage is mainly decided by capacitor esr and inductor ripple current. the output ripple voltage calculation can be further simplified to: for lower output ripple voltage across the entire operating temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum are recommended to be used as output capacitors. in a buck converter, output capacitor current is continuous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calculated by: usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. ? i l v o fl ? ---------- - 1 v o v in -------- - ? ?? ?? ?? ? = i lpeak i o ? i l 2 -------- + = ? v o ? i l esr co 1 8 fc o ? ? ------------------------- + ?? ?? ? = ? v o ? i l 1 8 fc o ? ? ------------------------- ? = ? v o ? i l esr co ? = i co_rms ? i l 12 ---------- =
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 10 of 15 loop compensation the AOZ1025D employs peak current mode control for easy use and fast transient response. peak current mode control eliminates the double pole effect of the output l&c filter. it greatly simp lifies the compensation loop design. with peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. the pole is dominant pole can be calculated by: the zero is a esr zero due to output capacitor and its esr. it is can be calculated by: where; c o is the output filter capacitor, r l is load resistor value, and esr co is the equivalent series resistance of output capacitor. the compensation design is actually to shape the converter control loop transfer function to get desired gain and phase. several different types of compensation network can be used for the AOZ1025D. for most cases, a series capacitor and resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. in the AOZ1025D, fb pin and comp pin are the inverting input and the output of internal error amplifier. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: where; g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, g vea is the error amplifier voltage gain, which is 500 v/v, and c c is the compensation capacitor. the zero given by the external compensation network, capacitor c c and resistor r c , is located at: to design the compensation circuit, a target crossover frequency f c for close loop must be selected. the system crossover frequency is where control loop has unity gain. the crossover is the also called the converter bandwidth. generally a higher bandwidth means faster response to load transient. however, the bandwidth should not be too high because of system stability concern. when designing the compensation loop, converter stability under all line and load condition must be considered. usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. the AOZ1025D operates at a fixed 500khz switching frequency. it is recommended to choose a crossover frequency equal or less than 40khz. the strategy for choosing r c and c c is to set the cross over frequency with r c and set the compensator zero with c c . using selected crossover frequency, f c , to calcu- late r c : where; f c is the desired crossover frequency. for best performance, f c is set to be about 1/10 of the switching frequency; v fb is 0.8v, g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, and g cs is the current sense circuit transconductance, which is 10.8 a/v the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of selected crossover frequency. c c can is selected by: the previous equation can also be simplified to: f p 1 1 2 ? c o r l ? ? ---------------------------------- - = f z 1 1 2 ? c o esr co ? ? ------------------------------------------------ = f p 2 g ea 2 ? c c g vea ? ? ------------------------------------------ - = f z 2 1 2 ? c c r c ? ? ----------------------------------- = f c 40 khz = r c f c v o v fb ---------- 2 ? c o ? g ea g cs ? ----------------------------- - ? ? = c c 1.5 2 ? r c f p 1 ? ? ----------------------------------- = c c c o r l ? r c --------------------- =
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 11 of 15 thermal management and layout consideration in the aoz1025 buck regulator circuit, the major power dissipating components are the aoz1025 output inductor, and low-side nmosfet. the total power dissipation of converter circuit can be measured by input power minus output power: the power dissipation of inductor can be approximately calculated by output curr ent and dcr of inductor: the power dissipation of low-side nmosfet can be approximately calculated by output current, rdson, and duty cycle (v o / v in ). the actual junction temperature can be calculated with power dissipation in the aoz1025 and thermal impedance from junction to ambient. the thermal performance of the AOZ1025D is strongly affected by the pcb layout. extra care should be taken by users during design to ensure that the ic will operate under the recommended environmental conditions. several layout tips are listed below for the best electric and thermal performance: 1. do not use thermal relief connection to the v in and the pgnd pin. pour a maximized copper area to the pgnd pin and the vin pin to help thermal dissipation. 2. input capacitor should be connected to the v in pin and the pgnd pin as close as possible. 3. a ground plane is preferred. if a ground plane is not used, separate pgnd from agnd and connect them only at one point to avoid the pgnd pin noise coupling to the agnd pin. 4. make the current trace from lx pins to l to co to the pgnd as short as possible. 5. pour copper plane on all unused board area and connect it to stable dc nodes, like v in , pgnd or sgnd. 6. keep sensitive signal trace away from switching node, lx. the copper pour area connected to the lx pin should be as wide as possible to avoid the switching noise on the lx pin coupling to other part of circuit. p total_loss v in i in v o i o ? ? ? = p inductor_loss i o 2 r inductor 1.1 ? ? = p inductor_loss i o 2 r inductor 1 v o v in -------- - ? ?? ?? ?? ? ? = t junction p total_loss p inductor_loss ? p nmos_loss ? ??? ja t amb + ? = figure 3. AOZ1025D (dfn 5x4) pcb layout
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 12 of 15 package dimensions, dfn-16 5x4 d l e2 aaa c ccc c ddd c bbb aaa c d/2 e/2 a3 b a1 unit: mm a a b e c cab seating plane notes: 1. all dimensions are in millimeters. 2. the location of the terminal #1 identifier and terminal numbering convention conforms to jedec publication 95 sp-002. 3. dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 4. coplanarity applies to the terminals and all other bottom surface metallization. 5. drawing shown are for illustration only. symbols a a1 a3 b d d2 d3 e e2 e l r aaa bbb ccc ddd dimensions in millimeters recommended land pattern side view top view bottom view min. 0.80 0.00 0.17 1.75 1.85 2.15 0.40 C C C C nom. 0.90 0.02 0.20 ref 0.25 5.00 bsc 1.90 2.00 4.00 bsc 2.30 0.50 bsc 0.50 0.30 ref 0.15 0.10 0.10 0.08 max. 1.00 0.05 0.35 2.00 2.10 2.40 0.60 C C C C symbols a a1 a3 b d d2 d3 e e2 e l r aaa bbb ccc ddd dimensions in inches min. 0.031 0.000 0.007 0.069 0.073 0.085 0.016 C C C C nom. 0.035 0.001 0.008 ref 0.010 0.197 bsc 0.075 0.079 0.157 bsc 0.091 0.020 bsc 0.020 0.012 ref 0.006 0.004 0.004 0.003 max. 0.039 0.002 0.014 0.079 0.083 0.094 0.024 C C C C 4 5 3 e d2 d3 index area (d/2xe/2) pin#1 ida 1 2 0.3 0.5 3.5 2.3 1.9 2.0 0.15 1.75 0.25 0.25 0.6
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 13 of 15 tape dimensions, dfn-16 5x4 r0.40 p0 k0 a0 e e2 d0 e1 d1 b0 package dfn 5x4 (12 mm) a0 b0 k0 e e1 e2 d0 d1 p0 p1 p2 t 5.30 0.10 0.10 4.30 0.10 1.20 min. 1.50 1.50 12.00 0.10 1.75 0.10 5.50 0.10 8.00 0.20 4.00 0.10 2.00 0.05 0.30 unit: mm t typ. 0.20 feeding direction tape leader/trailer and orientation 0.30 +0.10 / ?0 trailer tape (300mm min.) components tape orientation in pocket leader tape (500mm min.)
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 14 of 15 reel dimensions, dfn-16 5x4 view: c c 0.05 3-1.8 ?6 ?.2 6.45?.05 3- 2.9 ?.05 3-?/8" 3-?/4" 8.9?.1 11.90 14 ref 1.8 5.0 12 ref 41.5 ref 43.00 44.5?.1 2.00 6.50 10.0 10.71 10 3-?/16" r48 ref ?6.0?.1 2.20 6.2 ?3.00 ?1.20 ?7.0 r1.1 0 r3.10 2.00 3.3 4.0 6.10 0.80 3.00 8.00 +0.05 0.00 r0.5 1.80 2.5 38 44.5?.1 46.0?.1 8.0?.1 40 6 3- 3/16" r3.95 6.50 ?0.00 6.0 1.8 1.8 r1 8.00 0.00 -0.05 n=?00? a a a r121 r127 r159 r6 r55 p b w1 m ii i i 6.0? r1 zoom in iii zoom in ii zoom in a
AOZ1025D rev. 1.4 june 2012 www.aosmd.com page 15 of 15 package marking z1025di faywlt part number code underline denotes green product assembly lot code fab & assembly location year & week code as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. this data sheet contains preliminary data; supplementary data may be published at a later date. alpha & omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products ar e not authorized for use as critical components in life support devices or systems.

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